CD4017BE Decade Counter (DIP-16)

The CD4017BE Decade Counter is a CMOS decade counter with 10 decoded outputs in a DIP-16 package. It operates as a 5-stage Johnson counter and includes CLOCK, RESET, and CLOCK INHIBIT inputs. The CLOCK input uses Schmitt trigger action for pulse shaping and allows unlimited clock pulse rise and fall times. Each decoded output stays high for one full clock cycle. A CARRY-OUT signal completes one cycle every 10 input clock cycles and supports ripple-clock operation in a multi-device counting chain.

This CD4017BE Decade Counter is intended for sequential counting applications where decoded outputs and standard CMOS control inputs are required. It offers fully static operation, medium speed operation, and standardized symmetrical output characteristics. The device is also specified with 5-V, 10-V, and 15-V parametric ratings.

Features of CD4017BE Decade Counter DIP-16 - 3V To 18V

• 10 decoded outputs
• 5-stage Johnson counter
• CLOCK, RESET, and CLOCK INHIBIT inputs
• Schmitt trigger clock input
• Fully static operation
• Medium speed operation
• Symmetrical output characteristics
• CARRY-OUT output

Specifications of CD4017BE Decade Counter DIP-16 - 3V To 18V

• Supply voltage: 3 – 18 V
• Input clock frequency at VDD = 5 V: 2.5 MHz
• Input clock frequency at VDD = 10 V: 5 MHz
• Input clock frequency at VDD = 15 V: 5.5 MHz
• Voltage on VSS terminal: -0.5 to +20 V
• Input voltage for all inputs: -0.5 to VDD + 0.5 V
• Input current: ±10 mA
• Operating temperature: -55 to 125 °C
• Package: DIP-16
• 5-V, 10-V, and 15-V parametric ratings
• 100% tested for quiescent current at 20 V

How to Use CD4017BE Decade Counter DIP-16 - 3V To 18V

1. Apply the supply voltage within the specified range.
2. Connect the CLOCK input, RESET input, and CLOCK INHIBIT input as required.
3. Drive the CLOCK input with pulses to advance the counter.
4. Use the decoded outputs for sequential high-state timing.
5. Use the CARRY-OUT signal for ripple-clock operation in a counting chain.

More Info

• Each decoded output remains high for one full clock cycle.
• Counter advancement occurs on the positive clock signal transition when CLOCK INHIBIT is low.
• A high RESET signal clears the counter to zero.
• Decoded outputs are normally low and go high only in their assigned time slot.